1. Field of the Invention
The invention relates to improvement of miniaturized structures of memory cells and bit line structures in DRAMs (Dynamic Random Access Memory) and a manufacturing method thereof.
2. Description of the Background Art
In recent years, the demand for semiconductor memory devices has been rapidly expanding due to the remarkable spread of information equipment such as a computer. Furthermore, in a functional aspect, there is a need for a semiconductor memory device having a large storage capacity and capable of operating at high speed. Accordingly, there has been developed the technique of increased integration density and fast response or high reliability of a semiconductor memory device.
Semiconductor memory devices comprise a DRAM capable of randomly inputting/outputting storage information. Generally, a DRAM is structured by a memory cell array which is a storage region for storing a large amount of storage information and peripheral circuits required for input/output with an external device.
FIG. 15 is a block diagram showing a structure of a conventional general DRAM. In FIG. 15, a DRAM 50 includes a memory cell array 51 for storing a data signal of storage information, a row and column address buffer 52 for receiving an externally applied address signal for selecting a memory cell constituting a unit storage circuit, a row decoder 53 and a column decoder 54 for designating a memory cell by decoding the address signal, a sense refresh amplifier 55 for amplifying and reading out a signal stored in the designated memory cell, a data in buffer 56 and a data out buffer 57 for data input/output and a clock generator 58 for generating a clock signal.
The memory cell array 51 occupying a large area on the semiconductor chip is formed by a plurality of memory cells arranged in a matrix for storing unit storage information.
FIG. 16 is an equivalent circuit diagram of 4 memory cells included in the memory cell array 51. The illustrated memory cells are so-called single-transistor single-capacitor-type memory cells each structured by one MOS (Metal-Oxide-Semiconductor) transistor 15 and one capacitor 16 connected thereto. As the structure of this type of memory cell is simple, it is easy to enhance integration density of a memory cell array, so that it is widely used for a DRAM with a large storage capacity.
Memory cells of DRAMs can be divided into several types according to the structure of the capacitor for storing electric charge for information. A so-called stacked type memory cell is disclosed, for example, in Japanese Patent Publication No. 60-2784.
FIG. 17 is a sectional view of a structure of a stacked type memory cell stated in the article. As shown in FIG. 16, the memory cell includes one MOS transistor 15 and one capacitor 16. The MOS transistor 15 includes one pair of n.sup.+ impurity regions 7 and a gate electrode 17 constituted by part of a word line 17. The capacitor 16 has a layered structure of a lower electrode 8, a dielectric layer 9, and an upper electrode 10. The lower electrode 8 of the capacitor 16 is connected to one of the n.sup.+ impurity regions 7 of the MOS transistor 15. The capacitor 16 has its one end extending over the gate electrode 17 of the MOS transistor 15 and the other end extending over a field oxide film 3. It is intended to increase the electric charge storage capacity by forming the capacitor 16 in such a stepped configuration to increase the opposing area between the lower electrode 8 and the upper electrode 10. A bit line 14 is connected to the other n.sup.+ impurity region 7 of the MOS transistor 15. The bit line 14 is placed over the capacitor 16 with an interlayer insulating film 19 interposed therebetween. The bit line 14 is connected to the n.sup.+ impurity region 7 through a contact hole 12 formed in the interlayer insulating film 19.
However, an increased storage capacity in a DRAM has been needed more strongly, and correspondingly, miniaturization of an element structure of memory cells is required. The element structure of the MOS transistor 15 is further miniaturized with the need for miniaturization of the memory cell structure. One way for miniaturizing the MOS transistor 15 is to shorten the gate length and another way is to reduce the width of the impurity regions 7. In a stacked type memory cell as stated above, however, the lower electrode 8 of the capacitor 16 is directly in contact with one of the impurity regions 7 of the MOS transistor 15. Therefore, if the width of the impurity region 7 is reduced, the contact area between the lower electrode 8 of the capacitor 16 and the impurity region 7 is reduced, resulting in increase of the contact resistance. Accordingly, the width of the impurity regions 7 is controlled by the contact characteristic with the lower electrode 8 of the capacitor 16. A problem of an soft error arises, if the width of the impurity region 7 is large. A soft error is a phenomenon in which when .alpha. rays enter the silicon substrate, a malfunction of the device is caused. That is, when the .alpha. rays enter the silicon substrate, pairs of electrons and holes are generated. Then, the generated electrons enter the n-type impurity region 7 and are caught within the capacitor 16. If such a phenomenon is caused when there is no electron within the capacitor 16, it changes from a state without electrons to a state with electrons and inversion of information is caused, so that erroneous information is read out from the memory cells. Such an occurrence of a soft error is in proportion to the surface area of the n-type impurity regions 7, 7.
The bit line 14 is connected to the other impurity region 7 of the MOS transistor 15 through the contact hole 12. The contact hole 12 formed in the interlayer insulating layer 19 is formed by using photolithography involving mask alignment and an etching method. Therefore, the width of the impurity region 7 connected to this bit line 14 needs to be formed wide enough to absorb a mask alignment error at the time of forming the contact hole 12.
As stated above, in the conventional memory cell structure, it is difficult to reduce the width of the one pair of impurity regions 7, 7 of the MOS transistor 15.
Additionally, the bit line 14 is formed in such a largely stepped portion that it extends above the capacitor 16 and the contact portion thereof reaches a position of the substrate surface. Therefore, it is not preferable that a bit line with a miniaturized line width is formed in such a largely stepped region because coverage of bit line material becomes insufficient and accuracy of patterning the bit line material is decreased.